74ac14, 74act14 ? hex inverte r with schmitt trigger input ?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 february 2011 74ac14, 74act14 hex inverter with schmitt trigger input features i cc reduced by 50% outputs source/sink 24ma 74act14 has ttl-compatible inputs general description the 74ac14 and 74act14 contain six inverter gates each with a schmitt trigge r input. they are capable of transforming slowly changing input signals into sharply defined, jitter-free output signal s. in addition, they have a greater noise margin than conventional inverters. the 74ac14 and 74act14 have hysteresis between the positive-going and negative-going input thresholds (typi- cally 1.0v) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. ordering information device also available in tape and reel. specify by appending suffix letter ?x? to the ordering number. order number package number package description 74ac14sc m14a 14-lead small out line integrated circuit (soic) , jedec ms-012, 0.150" narrow 74ac14sj m14d 14-lead small outline pack age (sop), eiaj type ii, 5.3mm wide 74ac14mtc mtc14 14-lead thin shrink small ou tline package (tssop), jedec mo-153, 4.4mm wide 74act14sc m14a 14-lead small out line integrated circuit (soic) , jedec ms-012, 0.150" narrow 74act14mtc mtc14 14-lead thin shrink small ou tline package (tssop), jedec mo-153, 4.4mm wide
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 2 74ac14, 74act14 ? hex inverte r with schmitt trigger input connection diagram pin description logic symbol ieee/iec function table pin names description i n inputs o n outputs input output ao lh hl
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 3 74ac14, 74act14 ? hex inverte r with schmitt trigger input absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specif ications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?0.5v to +7.0v i ik dc input diode current v i ? ?0.5v ?20ma v i ? v cc + 1.5 +20ma v i dc input voltage ?0.5v to v cc + 1.5v i ok dc output diode current v o ? ?0.5v ?20ma v o ? v cc + 0.5v +20ma v o dc output voltage ?0.5v to v cc + 0.5v i o dc output source or sink current 50ma i cc or i gnd dc v cc or ground current per output pin 50ma t stg storage temperature ?65c to +150c t j junction temperature 140c symbol parameter rating v cc supply voltage ac 2.0v to 6.0v act 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ?40c to +85c
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 4 74ac14, 74act14 ? hex inverte r with schmitt trigger input dc electrical characteristics for ac notes: 1. all outputs loaded; thresholds on input associated with output under test. 2. maximum test duration 2.0ms, one output loaded at a time. 3. i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . symbol parameter v cc conditions t a ? +25c t a ? ?40c to +85c units (v) typ guaranteed limits v oh minimum high level output voltage 3.0 i out ? ?50a 2.99 2.9 2.9 v 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 i oh ? 12ma 2.56 2.46 4.5 i oh ? 24ma 3.86 3.76 5.5 i oh ? 24ma (1) 4.86 4.76 v ol maximum low level output voltage 3.0 i out ? 50a 0.002 0.1 0.1 v 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 i ol ? 12ma 0.36 0.44 4.5 i ol ? 24ma 0.36 0.44 5.5 i ol ? 24ma (1) 0.36 0.44 i in (3) maximum input leakage current 5.5 v i ? v cc , gnd 0.1 1.0 a v t+ maximum positive threshold 3.0 t a ? worst case 2.2 2.2 v 4.5 3.2 3.2 5.5 3.9 3.9 v t? minimum negative threshold 3.0 t a ? worst case 0.5 0.5 v 4.5 0.9 0.9 5.5 1.1 1.1 v h(max) maximum hysteresis 3.0 t a ? worst case 1.2 1.2 v 4.5 1.4 1.4 5.5 1.6 1.6 v h(min) minimum hysteresis 3.0 t a ? worst case 0.3 0.3 v 4.5 0.4 0.4 5.5 0.5 0.5 i old minimum dynamic 5.5 v old ? 1.65v max. 75 ma i ohd output current (2) 5.5 v ohd ? 3.85v min. ?75 ma i cc (3) maximum quiescent supply current 5.5 v in ? v cc or gnd 2.0 20.0 a
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 5 74ac14, 74act14 ? hex inverte r with schmitt trigger input dc electrical characteristics for act notes: 4. all outputs loaded; thresholds on input associated with output under test. 5. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a ? +25c t a ? ?40c to +85c units typ. guaranteed limits v ih minimum high level input voltage 4.5 v out ? 0.1v or v cc ? 0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out ? 0.1v or v cc ? 0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 0.8 v oh minimum high level output voltage 4.5 i out ? ?50a 4.49 4.34 4.4 v 5.5 5.49 5.4 5.4 4.5 v in ? v il or v ih , i oh ? ?24ma 3.86 3.76 5.5 v in ? v il or v ih , i oh ? ?24ma (4) 4.86 4.76 v ol maximum low level output voltage 4.5 i out ? 50a 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 4.5 v in ? v il or v ih , i ol ? 24ma 0.36 0.44 5.5 v in ? v il or v ih , i ol ? 24ma (4) 0.36 0.44 i in maximum input leakage current 5.5 v i ? v cc , gnd 0.1 1.0 a v h(max) maximum hysteresis 4.5 t a ? worst case 1.4 1.4 v 5.5 1.6 1.6 v h(min) minimum hysteresis 4.5 t a ? worst case 0.4 0.4 v 5.5 0.5 0.5 v t+ maximum positive threshold 4.5 t a ? worst case 2.0 2.0 v 5.5 2.0 2.0 v t? minimum negative threshold 4.5 t a ? worst case 0.8 0.8 v 5.5 0.8 0.8 i cct maximum i cc /input 5.5 v i ? v cc ? 2.1v 0.6 1.5 ma i old minimum dynamic output current (5) 5.5 v old ? 1.65v max. 75 ma i ohd 5.5 v ohd ? 3.85v min. ?75 ma i cc maximum quiescent supply current 5.5 v in ? v cc or gnd 2.0 20.0 a
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 6 74ac14, 74act14 ? hex inverte r with schmitt trigger input ac electrical characteristics for ac note: 6. voltage range 3.3 is 3.3v 0.3v. voltage range 5.0 is 5.0v 0.5v. ac electrical characteristics for act note: 7. voltage range 5.0 is 5.0v 0.5v. capacitance symbol parameter v cc (v) (6) t a ? +25c, c l ? 50pf t a ? ?40c to +85c, c l ? 50pf units min. typ. max. min. max. t plh propagation delay 3.3 1.5 9.5 13.5 1.5 15.0 ns 5.0 1.5 7.0 10.0 1.5 11.0 t phl propagation delay 3.3 1.5 7.5 11.5 1.5 13.0 ns 5.0 1.5 6.0 8.5 1.5 9.5 symbol parameter v cc (v) (7) t a ? +25c, c l ? 50pf t a ? ?40c to +85c, c l ? 50pf units min. typ. max. min. max. t plh propagation delay 5.0 3.0 8.0 10.0 3.0 11.0 ns t phl propagation delay 5.0 3.0 8.0 10.0 3.0 11.0 ns symbol parameter conditions typ units c in input capacitance v cc ? open 4.5 pf c pd power dissipation capacitance ac v cc ? 5.0v 25.0 pf act 80
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 7 74ac14, 74act14 ? hex inverte r with schmitt trigger input physical dimensions figure 1. 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ land pattern recommendation notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ab, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x145-14m e) drawing conforms to asme y14.5m-1994 f) drawing file name: m14arev13 pin one indicator 8 0 seating plane detail a scale: 20:1 gage plane 0.25 x 45 1 0.10 c c b c a 7 m 14 b a 8 see detail a 5.60 0.65 1.70 1.27 8.75 8.50 7.62 6.00 4.00 3.80 (0.33) 1.27 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 r0.10 r0.10 0.50 0.25
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 8 74ac14, 74act14 ? hex inverte r with schmitt trigger input physical dimensions (continued) figure 2. 14-lead small outline package (sop), eiaj type ii, 5.3mm wide package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 9 74ac14, 74act14 ? hex inverte r with schmitt trigger input physical dimensions (continued) figure 3. 14-lead thin shrink small outl ine package (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & botto m 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
?1988 fairchild semiconductor corporation www.fairchildsemi.com 74ac14, 74act14 ? rev. 1.7.2 10 74ac14, 74act14 ? hex inverte r with schmitt trigger input
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